1. Field of the Invention
This invention relates to a manufacturing process requiring lithography and, in particular, to monitoring of lithographic process conditions used in manufacturing microelectronic components and providing improved focus control.
2. Description of Related Art
Control of a lithographic imaging process requires the optimization of exposure and focus conditions in lithographic processing of product substrates or wafers. Generally, because of the variations in focus, patterns developed by lithographic processes must be continually monitored or measured to determine if the dimensions of the patterns are within acceptable range. The importance of such monitoring increases considerably as the resolution limit, which is usually defined as minimum features size resolvable, of the lithographic process is approached. The patterns being developed in semiconductor technology are generally in the shape of lines both straight and with bends, having a length dimension equal to and multiple times the width dimension. The width dimension, which by definition is the smaller dimension, is of the order of 0.1 micron to greater than 1 micron in the current leading semiconductor technology. Because the width dimension is the minimum dimension of the patterns, it is the width dimension that challenges the resolution limits of the lithographic process. In this regard, because width is the minimum and most challenging dimension to develop, it is the width dimension that is conventionally monitored to assess performance of the lithographic process. The term xe2x80x9cbiasxe2x80x9d is used to describe the change in a dimension of a feature from its nominal value. Usually the bias of interest is the change in the smallest of the dimensions of a given feature. Further, the term xe2x80x98biasxe2x80x99 is invariably used in conjunction with a process such as resist imaging, etching, developing etc. and described by terms such as image bias, etch bias, print bias, and the like.
Recent lithographic monitoring improvements have been in optical metrology which rely on human or machine-read visual measurement of targets which employ arrays of elements having line widths and spacing below the wavelength of the light used to make the measurements. Improvements in monitoring bias in lithographic and etch processes used in microelectronics manufacturing have been disclosed in U.S. Pat. Nos. 5,712,707; 5,731,877; 5,757,507; 5,805,290; 5,953,128; 5,965,309; 5,976,740; 6,004,706; 6,027,842; 6,128,089 and 6,130,750, the disclosures of which are hereby incorporated by reference. The targets and measurement methods of these applications rely on the increased sensitivity to focus variation provided by image shortening. Some of these types of targets use image shortening effects to make the visual measurements even though the individual array elements are not resolvable. Examples of such targets are disclosed in the aforementioned U.S. patents. Such targets permit visual monitoring of pattern features of arbitrary shape with dimensions on the order of less than 0.5 micron, and which is inexpensive to implement, fast in operation and simple to automate. These determine bias to enable in-line lithography/etch control using optical metrology, and wherein higher resolution metrology, such as SEM and/or AFM metrology, is required only for calibration purposes.
As described in particular in U.S. Pat. Nos. 5,953,128; 5,965,309; 5,976,740; 6,004,706; 6,027,842 and 6,128,089, the defocus of a lithographic image can be measured using dual-tone optical critical dimension (OCD) metrology. The problem remains, however, of providing a control system to feed back focus corrections to the lithography tool. The mere ability to determine that dose and/or focus is deviated from optimum is not sufficient in itself for closed-loop dose and focus control. For the most part, the prior art does not fully address 1) the need to determine both the sign and magnitude of a focus correction feedback to maintain an imaging system at optimum focus, 2) the need for adequate sensitivity to small defocus deviations from an optimum focus position, 3) the need to decouple and distinguish dose and focus variation, 4) the need for automated measurement and feedback. These requirements would be desirable for an automated focus control method and system.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an improved lithographic system for manufacturing microelectronic circuits.
It is another object of the present invention to provide improved focus control in lithographic processing.
A further object of the invention is to provide a focus control system for a lithography tool.
It is yet another object of the present invention to provide a lithographic focus control system which provides feedback to the lithography tool.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a process for controlling focus parameters in a lithographic process used in manufacture of microelectronic circuits. The process comprises initially providing a lithographic mask having a target mask portion containing a measurable dimension sensitive to defocus, projecting an energy beam through the target mask portion onto a first location of a substrate at a first focus setting, and lithographically forming a first target on the substrate corresponding to the first focus setting, the first target containing a measurable dimension sensitive to defocus. The process then includes projecting an energy beam through the target mask portion onto a second location of the substrate at a second focus setting, lithographically forming a second target on the substrate corresponding to the second focus setting, the second target containing a measurable dimension sensitive to defocus, and measuring the defocus sensitive dimension for each of the first and second targets on the substrate. The defocus sensitive dimension of the first and second targets are then compared and there is determined a desired focus setting of the energy beam based on the comparison of the dimensions of the first and second target. The process may be used to form focus setting targets on a semiconductor wafer for use in manufacture of microelectronic circuits.
Preferably, the targets comprise a plurality of spaced elements having essentially the same length and width and forming an array, ends of the individual elements being aligned to form first and second opposing array edges, the array elements having a predefined pitch. The defocus sensitive dimension measured and compared for each of the first and second targets on the substrate is the width of the array.
The target mask portion and the targets formed on the substrate may be characterized as each comprising a first area having a set of parallel array elements and a second, contrasting area having a set of contrasting parallel array elements parallel to the array elements on the first contrasting area, such that the target defocus sensitive dimension is measured by determining the distance between ends of the array elements on each of the first and second contrasting areas. More preferably, the targets comprise first and second complementary, tone reversed target portions. The first target portion comprises a plurality of spaced element shapes having essentially the same length and width and forming an array. The second target portion comprises a plurality of spaced element spaces having essentially the same length and width and forming an array, with the first target portion element shapes being of contrasting tone to the second target portion element spaces. Ends of the individual elements in each target portion are aligned to form first and second opposing array edges, with the array elements having a predefined pitch. The defocus sensitive dimension measured and compared for each of the first and second targets on the substrate is the width of the array.
The energy beam may be projected through the target mask portion onto a plurality of substrate locations at a plurality of focus settings to create a plurality of targets, so that the widths of the individual targets are measured and compared to determine the desired focus of the energy beam. The plurality of energy beam focus settings are preferably distributed at predetermined positive and negative increments around an initial focus setting. The process may be used to form a plurality of focus setting targets on a semiconductor wafer for use in manufacture of microelectronic circuits, wherein at least one of the focus setting targets is lithographically formed simultaneously with forming functional lithographic circuit elements on the wafer. In its preferred embodiment, the focus setting targets are formed at locations on the wafer away from the functional lithographic circuit elements such that the functional lithographic circuit elements may be separated from the focus setting targets when the wafer is cut apart.
The determination of the desired focus setting of the energy beam may be used to correct energy beam focus during lithographic forming of the functional circuit elements. Preferably, the determination of the desired focus setting of the energy beam is based on both the sign and magnitude of a focus correction feedback, and the focus correction feedback is based on a negative offset target defocus and a positive offset target defocus.
In another aspect, the present invention provides a process for forming focus setting targets on a semiconductor wafer and controlling focus parameters in a lithographic process used in manufacture of functional microelectronic circuit elements. The process comprises providing a lithographic mask having a target mask comprising first and second target mask portions. The first target mask portion comprises a plurality of opaque, spaced element shapes having essentially the same length and width and forming an array. The second target mask portion comprises a plurality of transparent, spaced element spaces having essentially the same length and width and forming an array. Ends of the individual elements in each target portion are aligned to form first and second opposing array edges, with the array elements having a predefined pitch, and the width between the array edges being sensitive to defocus when printed on a substrate. The process then includes projecting an energy beam through the target mask portion onto a first location of a substrate at a first focus setting, and lithographically forming a first target on the substrate corresponding to the target mask at a first focus setting, the first target having complementary, tone reversed target array portions containing a measurable width between the target array edges sensitive to defocus. The process further includes projecting an energy beam through the target mask portion onto a second location of the substrate at a second focus setting, and lithographically forming a second target on the substrate corresponding to the target mask at a second focus setting, the second target having complementary, tone reversed target array portions containing a measurable width between the target array edges sensitive to defocus. The process also includes measuring the width between the target array edges for each of the first and second targets on the substrate and comparing the target array edge width of the first and second targets; determining a desired focus setting of the energy beam based on the comparison of the dimensions of the first and second target array widths; and using the determination of the desired focus setting of the energy beam to correct energy beam focus during lithographic forming of the functional circuit elements.
The energy beam may be projected through the target mask portion onto a plurality of substrate locations at a plurality of focus settings to create a plurality of targets, wherein the widths of the individual target arrays are measured and compared to determine the desired focus of the energy beam. Preferably, the plurality of energy beam focus settings are distributed at predetermined positive and negative increments around an initial focus setting. The process may be used to form a plurality of focus setting targets on a semiconductor wafer for use in manufacture of microelectronic circuits, wherein at least one of the focus setting targets is lithographically formed simultaneously with, and at locations on the wafer away from, functional lithographic circuit elements on the wafer, such that the functional lithographic circuit elements may be separated from the focus setting targets when the wafer is cut apart. The determination of the desired focus setting of the energy beam may be based on both the sign and magnitude of a focus correction feedback, and the focus correction feedback may be based on a negative offset target defocus and a positive offset target defocus.
A dose correction may be made simultaneously with the focus correction based on a measurement of the first and second targets on the substrate.